Ð þí 080( ÿø,timll,omap3-devkit8000ti,omap3430ti,omap3 +7TimLL OMAP3 Devkit8000chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000 s/connector0 |/connector1cpus+cpu@0arm,cortex-a8…cpu‘•œcpu¨“à¶ÊÙpmu@54000000arm,cortex-a8-pmu‘T€áìdebugsssocti,omap-inframpu ti,omap3-mpuìmpuiva ti,iva2.2ìivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus‘há +öìl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ öHscm@2000ti,omap3-scmsimple-bus‘ + ö pinmux@30 ti,omap3-padconfpinctrl-single‘08+ý 2Pÿpinmux_twl4030_pinsm°AÙäpinmux_dss_dpi_pinsàm¤¦¨ª¬®°²´¶¸º¼¾ÀÂÄÆÈÊÌÎÐÒÔÖØÚÙøscm_conf@270sysconsimple-bus‘p0+ öp0Ùpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap‘°�pbias_mmc_omap2430ˆpbias_mmc_omap2430—w@¯-ÆÀÙêclocks+clock@68 ti,clksel‘hÇclock-mcbsp5-mux-fckÇti,composite-mux-clockÔmcbsp5_mux_fck•çÙ clock-mcbsp3-mux-fckÇti,composite-mux-clockÔmcbsp3_mux_fck•Ùclock-mcbsp4-mux-fckÇti,composite-mux-clockÔmcbsp4_mux_fck•çÙmcbsp5_fckÇti,composite-clock• Ùòclock@4 ti,clksel‘Çclock-mcbsp1-mux-fckÇti,composite-mux-clockÔmcbsp1_mux_fck•çÙ clock-mcbsp2-mux-fckÇti,composite-mux-clockÔmcbsp2_mux_fck•çÙ mcbsp1_fckÇti,composite-clock• Ùímcbsp2_fckÇti,composite-clock• Ùïmcbsp3_fckÇti,composite-clock•Ùðmcbsp4_fckÇti,composite-clock•Ùñclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single‘ \+ý 2Pÿpinmux_twl4030_vpins mÙåtarget-module@480a6000ti,sysc-omap2ti,sysc‘H `DH `HH `Lôrevsyscsyssþ  •œick+ öH ` aes1@0 ti,omap3-aes‘Pá&  +txrxtarget-module@480c5000ti,sysc-omap2ti,sysc‘H PDH PHH PLôrevsyscsyssþ  •œick+ öH P aes2@0 ti,omap3-aes‘Pá&AB+txrxprm@48306000 ti,omap3-prm‘H0`@á clocks+virt_16_8m_ckÇ fixed-clock5YÙosc_sys_ck@d40Ç ti,mux-clock•‘ @Ùsys_ck@1270Çti,divider-clock•çE‘pPÙ sys_clkout1@d70Çti,gate-clock•‘ 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Ôdpll4_m4_ck•EPÙ8dpll4_m3x2_mul_ckÇfixed-factor-clock•5grÙ6dpll4_m3x2_ck@d00Çti,gate-clock•6ç‘ |Ù2cm_96m_d2_fckÇfixed-factor-clock•1grÙ4omap_12m_fckÇfixed-factor-clock•7grÙXdpll4_m4x2_mul_ckÇti,fixed-factor-clock•8’ ­Ù9dpll4_m4x2_ck@d00Çti,gate-clock•9ç‘ |­Ù\dpll4_m5_ck@f40Çti,divider-clock•E?‘@PÙ:dpll4_m5x2_mul_ckÇti,fixed-factor-clock•:’ ­Ù;dpll4_m5x2_ck@d00Çti,gate-clock•;ç‘ |­Ùxdpll4_m6x2_mul_ckÇfixed-factor-clock•<grÙ=dpll4_m6x2_ck@d00Çti,gate-clock•=ç‘ |Ù>emu_per_alwon_ckÇfixed-factor-clock•>grÙ&clock@d70 ti,clksel‘ pÇclock-clkout2-src-gateÇ ti,composite-no-wait-gate-clockÔclkout2_src_gate_ck•-çÙAclock-clkout2-src-muxÇti,composite-mux-clockÔclkout2_src_mux_ck•- 1?ÙBclock-sys-clkout2Çti,divider-clock Ôsys_clkout2•@çE@Àclkout2_src_ckÇti,composite-clock•ABÙ@mpu_ckÇfixed-factor-clock•CgrÙDarm_fck@924Çti,divider-clock•D‘ $Eemu_mpu_alwon_ckÇfixed-factor-clock•DgrÙ'clock@a40 ti,clksel‘ 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Ôgpio3_ick•sçÙ˜clock-gpio2-ickÇti,omap3-interface-clock Ôgpio2_ick•sç Ù™clock-wdt3-ickÇti,omap3-interface-clock Ôwdt3_ick•sç Ùšclock-uart3-ickÇti,omap3-interface-clock Ôuart3_ick•sç Ù›clock-uart4-ickÇti,omap3-interface-clock Ôuart4_ick•sçÙœclock-gpt9-ickÇti,omap3-interface-clock Ôgpt9_ick•sç Ù�clock-gpt8-ickÇti,omap3-interface-clock Ôgpt8_ick•sç Ùžclock-gpt7-ickÇti,omap3-interface-clock Ôgpt7_ick•sçÙŸclock-gpt6-ickÇti,omap3-interface-clock Ôgpt6_ick•sçÙ clock-gpt5-ickÇti,omap3-interface-clock Ôgpt5_ick•sçÙ¡clock-gpt4-ickÇti,omap3-interface-clock Ôgpt4_ick•sçÙ¢clock-gpt3-ickÇti,omap3-interface-clock Ôgpt3_ick•sçÙ£clock-gpt2-ickÇti,omap3-interface-clock Ôgpt2_ick•sçÙ¤clock-mcbsp2-ickÇti,omap3-interface-clock Ômcbsp2_ick•sçÙ¥clock-mcbsp3-ickÇti,omap3-interface-clock Ômcbsp3_ick•sçÙ¦clock-mcbsp4-ickÇti,omap3-interface-clock Ômcbsp4_ick•sçÙ§emu_src_ckÇti,clkdm-gate-clock•tÙ(secure_32k_fckÇ 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2display1display2device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypassti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesti,use-ledsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsstatus#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-width#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,no-reset-on-initti,no-idleti,timer-alwonti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthdavicom,no-eepromgpmc,mux-add-datagpmc,wait-pingpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsvdds_dsi-supplyvdda_dac-supplyvdda-supplyremote-endpointti,channelsdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicegpiosdefault-statelinux,default-triggerti,modelti,mcbspti,audio-routinglinux,codewakeup-sourcepowerdown-gpiosdigitalddc-i2c-bus